Current processes for defining polysilicon (poly) gate electrodes involve the patterning of the gate through photolithography followed by an anisotropic poly etch which stops on the nitride (silicon nitride (SiN)) gate dielectric. However, etch selectivity between poly and nitride is poor hence stopping on the thin nitride gate dielectric becomes a significant problem. Poly edge GOI (gate oxide integrity) may become a problem if trenching of the silicon substrate occurs at the poly edge.
U.S. Pat. No. 5,963,818 to Kao et al. describes a method for forming an integrated circuit involves forming trench isolation regions and a damascene gate electrode region simultaneous with one another by over-lapping process steps using, inter alia, an inverse poly gate CMP.
U.S. Pat. No. 5,960,270 to Misra et al. describes a method for forming a metal gate MOS transistor using an inverse poly gate CMP. Source and drain regions are formed within a substrate self-aligned to a lithographically-patterned feature. The patterned feature is then removed and replaced by a metallic gate layer that is chemically mechanically polished (CMP) to form a metallic plug region that is either an inlaid or dual inlaid. The metallic plug region is self-aligned to the source and drain regions and preferably functions as a metal MOS gate region.
U.S. Pat. No. 5,943,576 to Kapoor describes a method of forming a MOS transistor having a narrow diffusion region that is smaller than the diffusion region defined using photoresist in a conventional CMOS processing. The method includes an inverse poly gate with sidewall spacers process.
U.S. Pat. No. 5,899,719 to Hong describes a method for making an FET (field effect transistor) having narrower gate electrodes and forming source/drain regions, including halo implants, in a more controlled manner. The method includes an inverse poly gate with sidewall spacers process.
U.S. Pat. No. 5,872,038 to Duane et al. describes a process for forming a semiconductor device having an elevated active region. A plurality of gate electrodes is formed on the semiconductor substrate an a thick oxide layer is disposed over the gate electrodes. A trench is formed in the thick oxide layer and is filled with a polysilicon material that is later doped to form an elevated active region above an active region of the substrate. The process includes a plain inverse poly gate CMP process.